This invention relates to electronic devices that are operated in synchronism with a clock signal, and more particularly to a system and method for compensating for variations in the propagation delay of clock signals in comparison to the propagation delay of other signals.
The operating speed of electronic devices, such as memory devices, can often be increased by synchronizing the operation of the device to a clock signal. By operating the device synchronously, the timing at which various function occur in the device can be precisely controlled thereby allowing the speed at which these functions are performed to be increased by simply increasing the frequency or speed of the clock signal. However, as the speeds of clock signals has continued to increase with advances in semiconductor fabrication techniques, the propagation delays of clock signals within integrated circuit devices have become a problem. More specifically, internal clock signals are often generated from an external clock signal applied to the integrated circuit device. These internal clock signals are coupled throughout the integrated circuit device to control the timing of a variety of circuits. The times required for the internal clock signals to propagate to these circuits is difficult to either control or predict. As clock speeds continue to increase, the unpredictable and/or uncontrolled variations in internal clock signal propagation times can cause internal clock signals to be applied to circuits either too early or too late to allow the circuits to properly perform their intended functions. This problem, known as xe2x80x9cclock skew,xe2x80x9d threatens to limit the speed at which integrated circuit devices can function.
Various solutions have been proposed to address this clock skew problems. Some of these solutions are described in Takanori Saeki et al., xe2x80x9cA Direct-Skew-Detect Synchronous Mirror Delay for Application-Specific Integrated Circuits,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 34, No. 3, March 1999. The article by Takanori Saeki et al. describes both open-loop and closed-loop clock skew compensation approaches. Closed-loop approaches include the use of phase-locked loops (xe2x80x9cPLLxe2x80x9d) and delay-locked loops (xe2x80x9cDLLxe2x80x9d) to synchronize the phase or timing of an internal clock signal to the phase or timing of an external clock signal used to generate the internal clock signal. These closed-loop approaches use a feedback signal to indicate the timing variations within the device. A phase comparator, such as a phase detector, is required to compare the phase or timing of the feedback signal to the phase or timing of a reference signal. Unfortunately, a significant amount of time may be required to achieve lock of the PLL or DLL.
Open-loop designs described in the Takanori Saeki et al. article include synchronized mirror delay (xe2x80x9cSMDxe2x80x9d) circuits and clock synchronized delay (xe2x80x9cCSDxe2x80x9d) circuits. CSD circuits generally include a variable delay line, usually a series of inverters, and latch circuits for selecting the output of one of these inverters as the delay line output. An internal clock signal is applied to the CSD circuit, and the magnitude of the delay provided by the CSD circuit is controlled in an attempt to set the phase or timing at which the internal clock signal is applied to an internal circuit. SMD circuits are basically the same as CSD circuits except that CSD circuits require the use of latches to store information. On the other hand, SMD circuits require specially shaped input clock signals. In order to generate internal clock signals on both the rising and falling edges of a clock signal (i.e., double data rate operation), SMD circuits, but not CSD circuits, require two variable delay lines, one for the clock signal and one for its compliment. In view of the similarity of CSD circuits and SMD circuits, they will be generically referred to herein as CSD/SMD circuits.
A conventional CSD/SMD circuit 10 described in the Takanori Saeki et al. article is shown in FIG. 1. An external clock signal XCLK is applied to an input buffer 12, and the output of the buffer 12 is applied to a delay model circuit 14. The output of the delay model circuit 14 is coupled through a measurement delay line to set a delay of a variable delay line 20. The delay of both the measurement delay line 16 and the variable delay line 20 is set to integer multiples of a clock period of the external clock signal less the delay of the delay model circuit 14, i.e., n*tCLKxe2x88x92dmdl, where n is an integer, tCLK is the period of the XCLK signal, and dmdl is the delay of the delay model circuit 14. The variable delay line 20 outputs a clock signal to a clock driver 24. The clock driver 24 then outputs an internal clock signal ICLK to an internal clock line 28. The internal clock line 28 is coupled to a number of internal circuits 32 through respective circuit paths, which are collectively known as a xe2x80x9cclock treexe2x80x9d 36.
The external clock signal XCLK is coupled through the input buffer 12 with a delay of d1, through the measurement delay line 16 with a delay of d2, through the variable delay line 20 with a delay of d3, and through the clock driver 24 with a delay of d4. For the phase of the internal clock signal ICLK to be synchronized to the phase of the external clock signal XCLK before the CSD/SMD circuit 10 has been locked, the sum of these delays, i.e., d1+dmdl+d2+d3+d4, should be equal to integer multiples of one period tCLK of the external clock signal XCLK.
In operation, the delay d3 of the variable delay line 20 is set in a conventional manner so that it is equal to the delay of the measurement delay line 16. The delay d2 of the measurement delay line 16 is set by conventional means to the difference between integer multiples of the period tCLK of the external clock signal XCLK and the delay dmdl of the delay model circuit 14, i.e., d2=n*tCLKxe2x88x92dmdl. Thus, after one clock period tCLK, the delay d3 of the variable delay line 20 has been determined. The total delay from the input of the input buffer 12 to the internal clock line 28 is given by the equation: d1+d3+d4. The delay dmdl of the delay model circuit 14 is set to the sum of the delay d1 of the input buffer 14 and the delay d4 of the clock driver 24. This can be accomplished by implementing the delay model circuit 14 with a xe2x80x9cdummyxe2x80x9d input buffer 42 and a xe2x80x9cdummyxe2x80x9d clock driver 44. The dummy input buffer 42 is preferably identical to the input buffer 12 and thus also provides a delay of d1.
Similarly, the dummy clock driver 44 is preferably identical to the clock driver 24 and thus also produces a delay of d4. Using the equation d3=d2=n*tCLKxe2x88x92dmdl, the above equation d1+d3+d4 for the total delay can be rewritten as: d1+n*tCLKxe2x88x92dmdl+d4. Combining this last equation and the equation dmdl=d1+d4 allows the equation for the total delay from the input of the input buffer 12 to the ICKL line 28 to be rewritten as: d1+n*tCLKxe2x88x92d1xe2x88x92d4+d4. This last equation can be reduced to simply n*tCLK, or 1 clock period of the external clock signal XCLK, assuming the delay of the delay model circuit 14 is less than a period of the external clock signal, i.e., dmdl less than tCLK. Thus, by using the delay model circuit 14 to model the delay d1 of the input buffer 12 and the delay d4 of the clock driver 24, the phase of the internal clock signal ICLK can be synchronized to the phase of the external clock signal XCLK. Moreover, the total lock time, including the delay through the delay model circuit 14 and the measurement delay line 16, is equal to d1+dmdl+d2+d3+d4, which can be reduced to 2n*tCLK. Therefore, this phase matching of the ICLK signal can be accomplished after only two periods of the external clock XCLK signal so that the integer xe2x80x9cnxe2x80x9d may be set equal to one.
Although the SMD/CSD circuit 10 shown in FIG. 1 can properly synchronize the phase of the internal clock signal ICLK to the phase of the external clock signal.XCLK, it does so only at the internal clock line 28. The SMD/CSD circuit 10 does not compensate for propagation delays in the clock tree 36 used to couple the internal clock signal ICLK from the internal clock line 28 to the internal circuits 32.
An SMD/CSD circuit 48 somewhat similar to the SMD/CSD circuit 10 can be used in a clock skew compensation circuit 50 as shown in FIG. 2 to compensate for propagation delays in a clock tree. The SMD/CSD circuit 48 is shown as being used to generate an internal clock signal from an external clock signal XCLK that is used to latch an external data signal DATA in a latch 52. The external data signal is coupled to the latch through a data input buffer 56 having a delay of d1. The external clock signal XCLK is applied to an input buffer 60 having a delay of d2, and the output of the input buffer 60 is applied through a delay model circuit 62 to a measurement delay line 64. The delay model circuit 62 has a delay of dmdl, and the measurement delay line 64 has a delay of d3. The output of the input buffer 60 is also applied to a variable delay line 70 that is controlled so that it has the same delay d3 as the measurement delay line 64, as previously explained. The output of the variable delay line 70 is applied to a clock driver 74 having a delay of d4. Finally, the internal clock signal has a propagation delay of d5 as it is coupled through a clock tree 78 from the clock driver 74 to the clock input of the latch 52.
The total delay from the input of the input buffer 60 to the clock input of the latch 52 is thus given by the equation: d2+d3+d4+d5 after the delay of the variable variable delay line 70 is determined. For the internal clock signal to enable the latch 52 to capture the data signal, the total delay should be reduced by the delay d1 of the DATA signal propagating through the data input buffer 56. The timing relationship between the XCLK signal and the DATA signal as they are applied to the latch 52 will then be the same as the timing relationship between the XCLK signal and the DATA signal as they are externally received. The XCLK signal is coupled to the latch with a total delay of: d2+d3+d4+d5. Substituting d3=[n*tCLKxe2x88x92dmdl] in the above equation yields for the total delay: d2+[n*tCLKxe2x88x92dmdl]+d4+d5. If the delay model circuit 62 models not only the delays of the input buffers 56, 60 and the clock driver 74, but also the delay d5 of the clock tree 78, the delay of the delay model circuit 62 is given by the formula: dmdl=d2-d1+d4+d5. The above equation for the total delay can then be expressed as: d2+[n*tCLKxe2x88x92d2+d1xe2x88x92d4xe2x88x92d5]+d4+d5. This equation can be reduced to simply n*tCLK+d1, or n periods of the XCLK signal plus the delay of the DATA signal through the input buffer 56. Letting n=1, the XCLK signal will thus be applied to the latch 52 one clock periods after the DATA signal is applied to the latch 52 so that the XCLK and DATA signals will have the same timing relationship at the latch 52 as the XCLK and DATA signals have at the external input terminals. To calculate the time for the SMD/CSD circuit 48 to achieve lock, the total delay time should be increased by the delay dmdl of the delay model circuit 62 and the delay d3 of the measurement delay line 64. Thus, the total time to achieve lock is d2+dmdl+(n*tCLKxe2x88x92dmdl)+(n*tCLKxe2x88x92dmdl)+d4+d5, which, for n=1 and dmdl less than tCLK, can be reduced using the formula dmdl=d2xe2x88x92d1+d4+d5 to 2*tCLK+d1.
The clock skew compensation circuits 50 improves the operation of synchronous digital circuits by attempting to compensate for propagation delays in a clock tree 78 coupled to a latch 52. As explained above, the circuit 50 attempts to compensate for clock tree propagation delays by attempting to model the propagation delay of the clock tree 78. However, it is significantly more difficult to model the propagation delay of the clock tree 78 compared to modeling the propagation delay of other circuits, such as the input buffers 56, 60 and the clock driver 74. The input buffers 56, 60 and clock driver 74, for example, can be modeled by simply including xe2x80x9cdummyxe2x80x9d buffers and drivers in the delay model circuit 62. But it is generally not practical to include an entire clock tree in the delay model circuit 62. Moreover, propagation delays can be different in different branches of the clock tree 78, and the propagation delay in even a single branch of the clock tree 78 can vary as a function of time and temperature, for example. With the continued increases in clock speed needed to increase the operating speed of integrated circuit devices, these variations in the propagation delays in the clock tree 78 can prevent the proper operation of integrated circuit devices.
There is therefore a need for a suitable system and method for compensating for clock signal skew as internal clock signals are coupled to various circuits through a clock tree.
A clock skew compensation circuit according to the present invention includes a synchronized mirror delay or clock synchronized delay having a measurement delay line and a variable delay line. A clock signal is coupled to the variable delay line of the synchronized mirror delay, optionally through a buffer that may delay the clock signal by a first delay value. A clock tree is coupled to an output terminal of the synchronized mirror delay. The clock tree generates a feedback signal that is coupled to an input terminal of the measurement delay line input terminal. The feedback signal corresponds to the propagation delay of the clock signal being coupled through the clock tree. The clock signal coupled through the clock tree may be used to capture a digital signal in a suitable circuit, such as a latch.